Continuing reduction of the minimum features produced by semiconductor processes and reduction in the size of the resulting devices has enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits and systems. As semiconductor process nodes continue to shrink, certain process features become difficult to monitor and thus, ensure uniform results. As the feature sizes for certain materials dictate device performance, the inability to observe or verify the thickness of layers, for example, at advanced semiconductor process nodes, creates problems in manufacturing uniformly performing devices.
In the use of non-volatile memory cells such as FLASH memory cells, a floating gate is provided that is surrounded by electrical insulator materials such as dielectric materials. Using hot electron injection or quantum tunneling, electrons may be stored on the floating gate. By using the floating gate as part of a MOS transistor in a memory cell, the cell may be programmed by adjusting the threshold voltage (Vt). When a read potential is provided to the floating gate by capacitively coupling the floating gate to an adjacent gate such as an erase gate or control gate, the stored data will either cause the cell to conduct and couple a bit line to a source connection, or not conduct, so that the memory cell can store a “1” or a “0”. To erase a programmed memory cell with a floating gate, a potential across a dielectric material such as a nitride or oxide is used to remove electrons from a floating gate to another gate conductor called an “erase gate” in an “ERASE” operation. The dielectric thicknesses between, for example the erase gate and the floating gate can therefore be critical to overall cell performance, affecting erase times (erase speed) and erase efficiency. In a typical “split gate” arrangement for FLASH cells, an erase gate electrode is formed between two adjacent memory cells each having floating gate electrodes that are surrounded by dielectric material. During an erase operation, electrons tunnel through a sidewall dielectric to the erase gate. However, this sidewall dielectric is formed in a manner that makes monitoring the thickness and uniformity of the dielectric during semiconductor processing impractical or impossible. Further, because this sidewall dielectric between the erase gate and the floating gate is exposed to various subsequent process steps after the dielectric formation, including etching and patterning steps for example, additional changes in the dielectric thickness after it is initially deposited can occur, and the changes to thickness in this dielectric affect cell erase operation and device speed.
As memory becomes increasingly important for portable devices, such as mobile phones, tablet computers, laptop computers, e-readers, and other battery operated devices, the use of non-volatile memory is increasingly prevalent. One important feature of non-volatile memory for battery powered devices is that the non-volatile memory cell retains its data even when the power in a device battery is lost. The data can be retained almost indefinitely as the floating gate that stores the charge corresponding to the stored data is electrically isolated. These non-volatile memory devices are continuously becoming larger, and lower in cost, and are currently displacing some, or all, of the data and program storage previously allocated to both dynamic RAM devices (DRAMs) and also hard disk drives (HDDs), for example, thus the need for efficiently manufactured, robust and cost effective non-volatile memory cells is increasing.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.